Jiantao Liu

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I am Jiantao Liu, a third-year Ph.D. student at ETH Zürich, supervisied by Prof. Dr. Lana Jospović. My research interests include High-Level Synthesis (HLS), Process-in-Memory (PIM), and Electronic Design Automation (EDA), with a broder focus on computer architecture and efficient computing systems.

I received my Master’s degree from ETH Zürich and my Bachelor’s degree from Huazhong University of Science and Technology.

I am currently a research intern with the CPU Architecture Team at Huawei Hong Kong Research Center (HKRC), where I work on system performance engineering, including evaluating the impact of new Arm ISA extensions and Scalable Matrix Extension (SME) on computational kernels, as well as analyzing agentic AI workloads for next-generation CPU architectures.

Feel free to reach out via email.

News

Our paper PNMAX on mapping-architecture co-exploration for processing near memory was accepted to MICRO 2026. :tada:
Our paper GLOW on glitch optimization with retiming for low power was accepted to ICCAD 2026. :tada:
GLOW received the Best Student Paper Award at IWLS 2026. :trophy:
Our paper GLOW on retiming for low power was accepted to IWLS 2026. :tada:
I joined the CPU Architecture Team at Huawei Hong Kong Research Center as a research intern, working on system performance engineering for next-generation CPUs. :rocket:

Publications

* denotes co-first authorship (equal contribution).

  1. MICRO
    PNMAX: Mapping-Architecture Co-Exploration Framework for Processing near Memory
    Chien-Yi Yang*, Jiantao Liu*, Yue Pan, and 3 more authors
    In Proceedings of the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct 2026
    To appear
  2. ICCAD
    GLOW: Glitch Optimization with Retiming for Low Power
    Jiantao Liu*, Carmine Rizzi*, Pravriti Jaipuriyar, and 4 more authors
    In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2026
    To appear
  3. IWLS
    GLOW: Glitch Optimization with Retiming for Low Power
    Jiantao Liu*, Carmine Rizzi*, Pravriti Jaipuriyar, and 4 more authors
    In Proceedings of the International Workshop on Logic and Synthesis (IWLS), Jun 2026
    Best Student Paper PDF
  4. ISCA
    OptiPIM: Optimizing Processing In-Memory Acceleration Using Integer Linear Programming
    Jiantao Liu*, Minxuan Zhou*, Yue Pan, and 3 more authors
    In Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA), Jun 2025
    Distinguished Artifact DOI PDF Code
  5. FPL
    Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits
    Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, and 1 more author
    In Proceedings of the 34th International Conference on Field-Programmable Logic and Applications (FPL), Sep 2024
    DOI PDF Code Website
  6. TCAS-II
    Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS
    Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, and 2 more authors
    IEEE Transactions on Circuits and Systems II: Express Briefs, Oct 2023
    DOI
  7. FPT
    Load-Store Queue Sizing for Efficient Dataflow Circuits
    Jiantao Liu, Carmine Rizzi, and Lana Josipović
    In Proceedings of the International Conference on Field-Programmable Technology (FPT), Dec 2022
    DOI PDF Code Website